1. Technical Field
The present disclosure relates to data transmission in a network comprising buses of different widths and particularly to systems on chip (SoCs) and networks on chip (NoCs).
2. Description of the Related Art
Systems on chip result from the integration into a same chip of several modules, which can comprise several processors, selected from a library of modules. The modules of a system on chip are not necessarily compatible between themselves particularly in terms of clock signal, communication protocol and interface bus width.
Generally, bridges that provide a communication protocol and/or bus width and/or clock frequency conversion are implemented to interconnect two interface buses that are not compatible between themselves. However, when the number of modules to be interconnected having incompatible interfaces is high, the number of bridges becomes excessive. Providing a high number of bridges indeed induces significant costs in terms of silicon surface, latency and energy consumption.
To facilitate the design of systems on chip and in particular the interconnection of the modules of such systems, networks have been developed. These networks, referred to as “networks on chip”, generally implement distributed communication means and are based on communication by packet switching and wormhole. Some of these networks comprise three types of communication components, i.e., network interfaces that provide the connection of a module with the network, routers that provide the transmission of packets between the network interfaces and other routers, and links between the routers and between the network interfaces and the routers. Each network interface particularly performs a protocol, and/or clock frequency, and/or data bus width conversion, between an interface bus of a module to which it is connected and a bus internal to the network. Furthermore, some modules have their own network, which is then linked to the network on chip. In addition, for the sake of improved optimization particularly of the chip surface area occupied by the system, it can be useful to provide different data bus widths according to the transmission rates of the modules to be interconnected. The result is that a data bus width is also capable of being converted in certain links between routers. As a result, several data bus width conversions may be applied to a message during the routing thereof between a transmitting module and a receiving module.
Two types of problem may arise during such a data bus width conversion. When converting a bus of a given width towards a bus with a smaller width, additional invalid data can be generated and transmitted into the network. It is true that a message transmitted by a data bus does not necessarily have a size corresponding to a whole number of times the width of the bus. The result is that one or more of the last words of the message transmitted by the data bus contain non-valid data. If this message is converted to be transmitted by a less wide data bus, the non-valid data transmitted may be alone in a word transmitted by the less wide data bus. This results in pointless consumption of bandwidth.
When converting towards a wider data bus, valid data can be placed on wrong data lines of the wider data bus. Such a conversion can therefore lead to errors in the reconstruction of messages transmitted by the network.
It is thus desirable to provide data bus width conversions so as to avoid these problems. It is also desirable to provide such conversions by implementing simple mechanisms and occupying as little surface as possible on the chip.